Intellectual Property Law

US Patent 7893492 - Nanowire mesh FET

MOSFET electronic designs are moving toward multi-gate and surrounding-gate designs to overcome short channel effects of planar transistors. This patent from IBM proposes a nanowire channel surrounding gate design with improved current carrying capability. Claim 1 reads:

1. A semiconductor structure comprising:

a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of a substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region;

a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region; and

a spacer located between each vertically stacked and vertically spaced apart semiconductor nanowire and between the gate region and the source region and drain region.

Full post as published by TinytechIP on February 27, 2011 (boomark / email).